./digital_soc_top.v
+incdir+../../verilog/core
../../verilog/core/cache.v
../../verilog/core/config.v
../../verilog/core/cpu_pipeline.v
../../verilog/core/cpu_top.v
../../verilog/core/ex_alu.v
../../verilog/core/ex_branch.v
../../verilog/core/ex_csr.v
../../verilog/core/ex_mem.v
../../verilog/core/inst_decoder.v
../../verilog/core/inst_fetch.v
../../verilog/core/mem_controller.v
../../verilog/core/registers.v
../../verilog/core/registers_csr.v
../../verilog/core/sys_bus.v
../../verilog/peripherals/digital/digital_flash.v
../../verilog/peripherals/digital/digital_ram.v
../../verilog/peripherals/gpio_controller.v
../../verilog/peripherals/peripherals_bus.v
../../verilog/soc/digital_soc.v